How do you write Verilog code for modified booth encoder?
1.booth encoder module:module booth_encode(input [2:0] X,output reg[2:0] SDN);always @ (X)beginif(X==8'b000) SDN=3'b000;else if(X==3'b001) SDN=3'b100;else if(X==3'b010) SDN=3'b100;else if(X==3'b011) SDN=3'b010;else if(X==3'b100) SDN=3'b011;else if(X==3'b101) SDN=3'b101;else if(X==3'b110) SDN=3'b101;else if(X==3'b111) SDN=3'b000;else SDN=3'bx;endendmodule2.Booth decoder module:module booth_decoder(input [7:0] Y,input [2:0] beo,output reg[8:0] bdo);reg [8:0]A;reg [7:0]X;always @(Y,beo)begincase(beo)3'b000:bdo=9'b000000000;3'b100:bdo={1'b0,Y};3'b101:beginX=(~Y)+1'b1;bdo={1'b1,X};end3'b010:bdo={Y,1'b0};3'b011:beginA={Y,1'b0};bdo=(~A)+1'b1;endendcaseendendmodule3.carry save adder module:module csa(input [14:0] P0,input [12:0] P1,input [10:0] P2,input [8:0] P3,output [14:0] P);wire sb,sc,sd,se,sf,sg,sh,si,sj,sk,sl,sm,sb1,sc1,sd1,se1,sf1,sg1,sh1,si1,sj1,sk1,sl1,sm1,ca,cb,cc,cd,ce,cf,cg,ch,ci,cj,ck,cl,cm,ca1,cb1,cc1,cd1,ce1,cf1,cg1,ch1,ci1,cj1,ck1,cl1,c00,c01,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11;hah01(P0[0],1'b0,P[0],c00);ha h02(P0[1],1'b0,P[1],c01);ha h1(P0[2],P1[0],P[2],ca);ha h2(P0[3],P1[1],sb,cb);fa f01(P0[4],P1[2],P2[0],sc,cc);fa f02(P0[5],P1[3],P2[1],sd,cd);fa f03(P0[6],P1[4],P2[2],se,ce);fa f04(P0[7],P1[5],P2[3],sf,cf);fa f05(P0[8],P1[6],P2[4],sg,cg);fa f06(P0[9],P1[7],P2[5],sh,ch);fa f07(P0[10],P1[8],P2[6],si,ci);fa f08(P0[11],P1[9],P2[7],sj,cj);fa f09(P0[12],P1[10],P2[8],sk,ck);fa f010(P0[13],P1[11],P2[9],sl,cl);fa f011(P0[14],P1[12],P2[10],sm,cm);ha h3(sb,ca,P[3],ca1);ha h4(sc,cb,sc1,cb1);ha h5(sd,cc,sd1,cc1);fa f11(se,cd,P3[0],se1,cd1);fa f12(sf,ce,P3[1],sf1,ce1);fa f13(sg,cf,P3[2],sg1,cf1);fa f14(sh,cg,P3[3],sh1,cg1);fa f15(si,ch,P3[4],si1,ch1);fa f16(sj,ci,P3[5],sj1,ci1);fa f17(sk,cj,P3[6],sk1,cj1);fa f18(sl,ck,P3[7],sl1,ck1);fa f19(sm,cl,P3[8],sm1,cl1);ha h6(sc1,ca1,P[4],c1);fa f1(c1,sd1,cb1,P[5],c2);fa f2(c2,se1,cc1,P[6],c3);fa f3(c3,sf1,cd1,P[7],c4);fa f4(c4,sg1,ce1,P[8],c5);fa f5(c5,sh1,cf1,P[9],c6);fa f6(c6,si1,cg1,P[10],c7);fa f7(c7,sj1,ch1,P[11],c8);fa f8(c8,sk1,ci1,P[12],c9);fa f9(c9,sl1,cj1,P[13],c10);fa f10(c10,sm1,ck1,P[14],c11);endmodule4.half adder module:module ha(input a,input b,output sum,output carry);xor x1(sum,a,b);and a1(carry,a,b);endmodule5.full adder module:module fa(input a,input b,input c,output sum,output carry);wire w1,w2,w3;ha h1(a,b,w1,w2);ha h2(w1,c,sum,w3);or o1(carry,w2,w3);endmodule6.Final module:module final_module(input [7:0] X,input [7:0] Y,output [14:0] P);reg [2:0]a,b,c,d;wire [2:0]sdn1,sdn2,sdn3,sdn4;wire [8:0]p0,p1,p2,p3;wire [14:0]p00;wire [12:0]p01;wire [10:0]p02;always @(X)begina={X[1],X[0],1'b0};b={X[3],X[2],X[1]};c={X[5],X[4],X[3]};d={X[7],X[6],X[5]};endbooth_encode b1(a,sdn1);booth_decoder d1(Y,sdn1,p0);assign p00=p0[8]?{6'b111111,p0}:{6'b000000,p0};booth_encode b2(b,sdn2);booth_decoder d2(Y,sdn2,p1);assign p01=p1[8]?{4'b1111,p1[8:0]}:{4'b0000,p1[8:0]};booth_encode b3(c,sdn3);booth_decoder d3(Y,sdn3,p2);assign p02=p2[8]?{2'b11,p2}:{2'b00,p2};booth_encode b4(d,sdn4);booth_decoder d4(Y,sdn4,p3);csa c1(p00,p01,p02,p3,P);endmodule
