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The 2's complement of a number in n bits is that number when added to the original number results in 0 in n bits.

It is used to represent negative numbers so that with n bits you have 2ⁿ⁻¹ each of positive and negative numbers - the top bit is used to specify if the number is negative and if set, the number is stored in 2's complement of the positive number. As a result of this, when adding or subtracting positive and negative numbers, there is no need to worry about the sign as it is handled automatically.

To convert a binary number to its 2's complement invert all the bits and add 1 (this is the same as subtracting it from 2 to the power of one more than the number of bits used to store the number)

eg in 8 bits, the 2's complement of 42 (0x2A = 0010 1010) is:

Invert all the bits: 0010 1010 → 1101 0101

add 1: 1101 0101 + 1 = 1101 0110 (0xD6)

→ the 2's complement of 42 in 8 bits is 214 (= -42)

Note: 42 + 214 = 256 = 1 0000 0000 in binary which has the bottom 8 bits 0.

When doing arithmetic with signed numbers, there is usually an overflow flag (V) in the processor which is set if the operation results in a carry from the top-1 bit to the top bit.

eg in 8 bits when using signed numbers 42 (0010 1010) + 100 (0110 0100) = 142 (1000 1110) but as it has the top bit set it represents a negative number (142: 1000 1110 → 0111 0001 + 1 = 0111 0010 = -114) - to indicate that the number (could) represent a negative number not a positive number the processor may set the overflow flag.

The maximum positive number in 8 bits is 127 (0111 1111), the maximum negative number is 1000 0000 → 0111 1111 + 1 = 1000 0000 = -128; ie the range of possible numbers when using 8 bits to represent a signed number is -128 to +127

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7y ago

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